In a logic circuit or the like, a plurality of cells are combined, with one inverter circuit being defined as one cell. In a cell of an inverter circuit, if it is assumed that cells are arranged in an X-Y plane, a power supply interconnection and a ground interconnection spaced apart from each other extend in an X-axis direction. An n-channel type field effect transistor and a p-channel type field effect transistor are connected in series between the ground interconnection and the power supply interconnection. In addition, a gate interconnection portion extends in a Y-axis direction orthogonal to the X-axis direction.
A size of a cell is represented by a pitch and a grid. A pitch defines a length in the X-axis direction and a grid defines a length in the Y-axis direction. A length of 1 pitch is equal to a length of 1 grid. Normally, 1 pitch is a minimum pitch of a first interconnection, and it is defined as a length which is a sum of an interconnection width of the first interconnection and an interval between adjacent first interconnections.
Cells of conventional inverter circuits include a cell of 3 pitches and 9 grids, a cell of 3 pitches and 7 grids, or the like. Here, if it is assumed that a first interconnection has an interconnection width L of 180 nm and an interval S of 180 nm, a minimum pitch of the first interconnection is 360 nm, and a cell of 3 pitches and 7 grids has a length in the X-axis direction of 1080 nm (360 nm×3) and a length in the Y-axis direction of 2520 nm (360 nm×7). It is noted that, for example, Japanese Patent Laying-Open No. 11-330461 (PTD 1) and Japanese Patent Laying-Open No. 05-198593 (PTD 2) are exemplified as documents disclosing a field effect transistor applied to such a cell of an inverter circuit.